1. Field of Invention
The present invention relates to a semiconductor manufacturing method. More particularly, the present invention relates to a method of manufacturing a flash memory.
2. Description of Related Art
Flash memory is a type of device that permits multiple accesses, read-outs and erases. Furthermore, data stored within the device is retained even after power to the device is cut off. With such big advantages, flash memory is one of the most useful non-volatile memories in personal computers and electronic equipment.
A typical flash memory device has doped polysilicon floating gate and control gate. The floating gate and the control gate inside the device are isolated from each other by a dielectric layer. To write/erase data into a flash memory, a bias voltage is applied to the control gate and the source/drain region and hence electrons are injected into the floating gate or pulled out of the floating gate. To read data from the flash memory, an operating voltage is applied to the control gate. Since the charging state of the floating gate directly affects the conduction of the channel underneath, a data value of “1” or “0” can be determined.
To erase data from the flash memory, relative potential of the substrate, the drain (source) region or the control gate is raised so that tunneling effect sets in to force the trapped electrons within the floating gate into the substrate or drain (source) terminal through the tunneling oxide layer (that is, carrying out a substrate erase or drain (source) side erase). Alternatively, the electrons trapped within the floating gate pass through the dielectric layer and transfer to the control gate. Since the quantity of electrons bled out from the floating gate when erasing data from the flash memory is difficult to control, an excessive amount of electrons may flow out from the floating gate resulting in a net positive charge. This condition is called over-erase. When over-erase is excessive, the channel underneath the floating gate may conduct before the application of an operating voltage to the control gate and hence ultimately lead to a data read-out error. To minimize data errors due to an over-erased floating gate, a high-density flash memory with a three-layered gate is developed.
FIGS. 1A to 1C are schematic cross-sectional views showing the steps for producing a conventional flash memory. As shown in FIG. 1A, an insulating layer (not shown) and a conductive layer (not shown) is formed over a substrate 100. The conductive layer and the insulating layer are patterned to form a dielectric layer 102 and a select gate 104. Thereafter, a tunneling oxide layer 106 is formed over the substrate 100 and an inter-gate dielectric layer 108 is formed over the select gate 104.
As shown in FIG. 1B, a conductive layer or a doped polysilicon layer is formed over the substrate 100. The conductive layer 110 is patterned to form a plurality of longitudinal strips such that a portion of the conductive layer 110 lies above the select gate 104. Another inter-gate dielectric layer 112 is formed over the conductive layer 110. Thereafter, another conductive layer 114 or doped polysilicon layer is formed over the inter-gate dielectric layer 112.
As shown in FIG. 1C, the conductive layer 114, the inter-gate dielectric layer 112, the conductive layer 110 and the tunneling oxide layer 106 are patterned to form a control gate 114a, an inter-gate dielectic layer 112a, a floating gate 110a and a tunneling oxide layer 106a. The select gate 104, the floating gate 110a and the control gate 114a together constitute a gate structure. Thereafter, a source region 116 and a drain region 118 are formed in the substrate 100 on each side of the gate structure.
In the process of forming the control gate 114a, the channel regions 120a, 120b underneath the floating gate 110a is difficult to define due to possible mask misalignment between the floating gate 110a and the select gate 104. In other words, if the patterned floating gate 110a is misaligned length between the channel region 120a and the channel region 120b will never be identical. Because channel length of two neighboring memory cells using the same common source region are non-identical, memory cell programming will be non-symmetrical. Ultimately, operating speed of the memory cells will have to slow down.